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ASIC and FPGA RTI engineers have
completed many successful ASIC and FPGA designs. RTI is a proud partner of the Altera ACAP program. This partnership provides our customers many
benefits in the Altera product line, but RTI is not limited to Altera
FPGA’s. We have successfully completed projects
in the following technologies:
Some of
the products that RTI engineers have completed include, but are not limited to:
Control Logic
A Xilinx
4010 FPGA was used to interface with the IBM PowerPC 603’s SIO bus. This FPGA then connects with other FPGA’s
and/or ASIC’s allowing the PowerPC to interface with memory and external
devices. The original design allowed
the PowerPC to communicate with the VMEbus; however later design interfaces
include the PCI bus, and other standard and non-standard buses. The Xilinx design was ported to a radiation
hardened Actel 1280 FPGA. The Actel
design is still being used in numerous space probe designs. The Mars Path Finder and Cassini Probe are
some of the programs which have successfully used this design. Signal Processing
Some
examples of programs which RTI engineers have been involved are listed below. The FIR
and Timing (FAT) ASIC provides a 7 tap symmetric FIR filter along with timing
required for the communications channel.
RTI engineers were involved with the modification FAT ASIC with Enhanced
Requirements (FATER) to allow for the TDMA signal shaping required for QPSK
satellite ground terminal station. The
digital beamforming (BFN) ASIC design included four programmable beamformming
processors. The BFN received 128 serial
inputs from DeMux ASICs. Each processor
read the address of the serial input and the associated coefficients to form
the output beams. Each processor could
generate up to four beams. The output
data was then transmitted over 128 serial outputs to the data routers The
12-Point Inverse Discrete Fourier Transform (IDFT) was a core designed for a
127 tap Poly Phase FIR Filter. The IDFT
was implemented using the prime factor method, and was implemented using four
3-point Butterfly and three 4-point Butterfly elements. The IDFT design included programmable input
and output vector bit widths. Each
stage provided options that allowed for input registers to be instantiated or
not. The core was targeted for an ASIC
in IBM R25 logic, but was not specific to that technology. Data Formatting
The Air
Interface Data Formatter FPGA formatted data from a proprietary backbone
network to the format required by a TDMA over the air data network. Guard band bits were added to transmit data
packets into TDMA format, while receive data was E1/T1
payload Formatter FPGA formatted data from a proprietary backbone network to
the format required by either the E1 or T1 standards. Data packets were transmitted or received from DS0 timeslot(s)
that were assigned by an external processor.
The operational mode (E1 or T1) was selected by configuration registers. ATM payload
Formatter formatted data from a proprietary backbone network to the format
required by the ATM standard. The OC12
Receive FPGA receives OC12 packets from a Packet Over Sonnet interface chip and
converts the data to a Ethernet MAC format over a proprietary router backbone
interface chip. The OC12 Transmit FPGA receives Ethernet MAC format frames
from a proprietary router backbone interface and converts the data to OC12
packets and sends the data to a Packet Over Sonnet interface chip. |
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