RTI has successfully completed projects with many customers.   RTI has extensive expertise in the following areas:

• High Speed Multi-Protocol Switch Chips
• Satellite Beamforming ASICs
• Custom Hardware Device Boards and Controllers
• Packet Radio Hardware
• Media Converters
• Digital Signal Processing for Signal Intelligence Systems
• Set Top Box and Audio/Video Chipsets
• Optical Carrier Chips
• Cellular and Digital Handset Chips

 

Some of the specific tasks that we have performed are:

 

Hughes Network Systems       

·      Copernicus                    

RTI engineers have supported the following tasks:

A solicited proposal for Project Management, SOW, and manpower planning for Device Verification Testing for a new ASIC design.

Engineering design and prototype development of a custom high performance RTOS to run as firmware on the new ASIC in several implementations of a network processor based on Tensilica/Xtensa and Power PC 405G embedded cores providing specialized network packet management services to various components in the System-On-Chip (SOC) design.

 

·      Mt. Everest                    

RTI was part of the hardware verification team for Top Level Simulations and Design Verification Tests, which proved and eliminated design errors prior to manufacturing the chip.

RTI analyzed and identified the required Design Verification Tests to fully prove the Transport, security, PCI interface and Demodulator sections prior to production.

FPGAs were developed to support hardware testing.

 

·      Packet Radio Channelizer Unit    

Design leads for high-speed digital design of a packet radio, common hub gateway station.

Design analysis for a proprietary high-speed bus on a cPCI midplane

 

·      Mobile Satellite              

RTI engineers have supported the following tasks:

Design lead on FATER (FIR And Timing Enhanced Requirements) ASIC

Lab bring-up and conformance testing of Gateway Stations for Thuraya, Inmarsat and ICO systems.

 

·      Point To Multipoint          

RTI engineers have supported the following tasks:

Air interface payload formatter FPGA development

T1/E1 payload formatter FPGA development

ATM payload formatter FPGA development

 

Lockheed Martin                     

·         Asian Cellular Satellite System (ACeS)

RTI engineers provided lab bring up and conformance testing along with extensive software development support.

 

·         Gravity Probe Satellite   

RTI engineers provided lab bring up and conformance testing.

 

·         Digital Beamformer ASIC           

RTI engineers provided the ASIC lead role.

The beamformer ASIC was to be used in an upgraded version of the ACeS satellite.

 

BAE Systems

·         LEO One Satellite         

System development and Card design.

 

·         DRP Satellite                

System development

Backplane and Card design

System bring-up and test

 

·         CSPAD                        

Development of ASIC cores including design and simulation

 

·         Operations                   

Bring up and manufacturing verification of satellite cards

 

Nortel Networks                      

·         OC12 Receive FPGA     

FPGA design and simulation: The OC12 Receive FPGA receives OC12 packets from a Packet Over Sonnet interface chip and converts the data to a Ethernet MAC format over a proprietary router backbone interface chip.

 

·      OC12 Transmit FPGA     

FPGA design and simulation: The OC12 Transmit FPGA receives Ethernet MAC format frames from a proprietary router backbone interface and converts the data to OC12 packets and sends the data to a Packet Over Sonnet interface chip.